An 84dB-SNDR Low-OSR 4th-Order Noise-Shaping SAR with an FIA-Assisted EF-CRFF Structure and Noise-Mitigated Push-Pull Buffer-in-Loop Technique

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With the combined merits of the SAR and the ΔΣ ADCs, the noise-shaping (NS) SAR architecture can achieve high resolution with a mild OSR, making it versatile for a wide range of applications. Nonetheless, designing a highly power-efficient NS-SAR under relatively low OSRs (<8) can be challenging. It requires the design to concurrently address two key considerations. The first is to implement high-order optimized NS with simple and low-power hardware that maximally preserves a SAR’s efficient nature. In this regard, two recent works report 4th-order NS using a cascaded EF structure [1] and an FVF-assisted CIFF structure [2] respectively, both allowing aggressive NTFs to be realized with simple open-loop amps. However, they still employ static amps/buffers, which limit the power improvement. Also, the lack of NTF optimization makes them nonideal for low OSR designs. The second concern is the growing kT/C noise contribution under low OSR and the related large stress on the input driver. To alleviate this issue, ref [3] presents an NS-SAR with a loop-embedded input buffer that decouples the input capacitance from the kT/C noise constraint; but it suffers from large noise penalty introduced by the buffer and the separated CDAC. Alternatively, a sampling noise cancellation (SNC) technique is proposed in [4] to facilitate a smaller CDAC value. However, owing to imperfect cancellation caused by circuit non-idealities, the CDAC can remain considerably large.

IEEE International Solid-State Circuits Conference (ISSCC) 2022, accepted
Supplementary notes can be found here, including our ISSCC 2022 Presentation, and the main page on IEEE Xplore.
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Zhe Liu
Zhe Liu
DRAM Design Verification Engineer