Zhe Liu

Zhe Liu

DRAM Design Verification Engineer

Micron Technology Inc.

Biography

Hello, Welcome to my page!

My name is Zhe Liu! I graduated from Georgia Tech in 2022 with a MSECE degree with a passion in VLSI design. I am a DRAM Design Verification Engineer at Micron Technology at Atlanta working on pre-silicon DDR5 design and verification. We are responsible for delivering cutting-edge, industry leading DRAM solution that can support complex and high-performance compute SoC functions in the most efficient manner.

I very much look forward to the challenge and exciting career in engineering! Please feel free to reach out to me

Interests
  • Identify and develop coverage measures for stimulus and corner-cases
  • Debug failure, purpose circuit improvement methodology to deliver functionally correct design
  • Cooperate with design engineers, peoduct engineer, and other relevant functions to solve technical issues for quality
  • Innovate to improve verification efficiency

Education

 
 
 
 
 
Georgia Institute of Technology
Master of Science in Electrical and Computer Engineering
Georgia Institute of Technology
Aug 2020 – May 2022 Atlanta, GA
 
 
 
 
 
Virginia Tech
Bachelor of Science in Electrical Engineering
Virginia Tech
Aug 2016 – May 2020 Blacksburg VA

Engineering Projects

1-Bit SRAM Cell in 45-nm CMOS Technology with Integrated Dynamic Power Supply
Dynamic Cell Vcc proves the improvement in both Read and Write margins and leakage saving
Zhe Liu, Dylan Nektalov
Last updated on Feb 12, 2022 8 min read SRAM, Validation
A 12-bit Two-Stage Pipelined SAR ADC design
This page presents a two stage fully differential pipelined SAR ADC design that I worked on during Spring 2021
Zhe Liu, Shida Zhang
Last updated on Feb 12, 2022 4 min read ADC
A 12-bit Two-Stage Pipelined SAR ADC design
FetoMic
A Phonocardiography Approach to Low-Cost Fetal Heart Monitoring
Zhe Liu
Last updated on May 20, 2021 1 min read FetoMic

Publications

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Tian Xie, Tzu-Han Wang, Zhe Liu, Shaolan Li (2022). An 84-dB-SNDR Low-OSR Fourth-Order Noise-Shaping SAR With an FIA-Assisted EF-CRFF Structure and Noise-Mitigated Push-Pull Buffer-in-Loop Technique.

DOI

Tzu-Han Wang, Tian Xie, Zhe Liu, Shaolan Li (2022). An 84dB-SNDR Low-OSR 4th-Order Noise-Shaping SAR with an FIA-Assisted EF-CRFF Structure and Noise-Mitigated Push-Pull Buffer-in-Loop Technique. ISSCC 2022.

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Notes

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