Posts

1-Bit SRAM Cell in 45-nm CMOS Technology with Integrated Dynamic Power Supply
Dynamic Cell Vcc proves the improvement in both Read and Write margins and leakage saving
刘哲, Dylan Nektalov
最近更新于 Apr 28, 2022 8 分钟阅读时长 SRAM, Validation
A 12-bit Two-Stage Pipelined SAR ADC design
This page presents a two stage fully differential pipelined SAR ADC design that I worked on during Spring 2021
刘哲, Shida Zhang
最近更新于 Apr 28, 2022 4 分钟阅读时长 ADC
A 12-bit Two-Stage Pipelined SAR ADC design
FetoMic
A Phonocardiography Approach to Low-Cost Fetal Heart Monitoring
刘哲
最近更新于 Apr 28, 2022 1 分钟阅读时长 FetoMic